In the filed of digital video data, Low Voltage Differential Signaling (LVDS) streams may be implemented for transmitting data, e.g., image data. For example, in Liquid Crystal Display (LCD) systems it may be required to transfer a large amount of image data at a relatively high data rate. Transferring the image data at a high data rate may result in an increased level of electro-magnetic interference (EMI), e.g., if a parallel interface is used for transferring the image data.
A typical LCD system may implement one or more LVDS streams to transfer image pixel data between an input and a timing controller (TCON) of the LCD system. The LCD system may include, for example, a LVDS transmitter to convert input image data, e.g., including image pixel data in a Complementary-Metal-Oxide-Semiconductor/Transistor-Transistor-Logic (CMOS/TTL) format, into image data in a LVDS format to be transferred over a LVDS stream including, e.g., four or five LVDS data channels. The stream may include an additional LVDS channel (“the clock LVDS channel”) to transfer a phase-locked transmit clock (“the LVDS clock”) in parallel with the LVDS data channels. Each one of the LVDS data channels may be adapted to transfer 7 bits during each clock cycle of the transmit clock. Accordingly, the LVDS stream may be able to transfer a maximum of 28 or 35 bits during each clock cycle of the transmit clock, e.g., if the stream includes four or five data channels, respectively. A typical LVDS stream may implement a transmit clock having a clock frequency of 135 Mega Hertz (MHz). Accordingly, a single typical LVDS channel may have a maximal data transmission rate of 135*7=945 Mega bit per second (Mbps). A typical LVDS stream including four data channels may have a maximal data transmission rate of 945*4=3.78 Giga bit per second (Gbps), and a typical LVDS stream including five data channels may have a maximal data transmission rate of 945*5=4.72 Gbps.
In conventional LCD systems each pixel is reproduced using three primary colors, namely red (R), Green (G) and Blue (B). Each primary color component may be represented by an 8-bit value.
Typically, the LVDS transmitter transmits data of a whole pixel per LVDS clock. During each clock cycle, the LVDS transmitter transmits 27 bits, including 24 bits representing data of a single pixel, e.g., 8 bits representing the red component of the pixel, 8 bits representing the green component of the pixel, and 8 bits representing the blue component of the pixel; and 3 bits of LCD timing and control data, e.g., representing Data-End (DE), Horizontal Synchronization (HSYNC) and Vertical Synchronization (VSYNC) information. Thus, conventional RGB LCD systems implement only 27/28 of the available bandwidth of the LVDS stream.
For example, the LVDS transmitter may transmit the RGB pixel data in the following format:
TABLE 1TX bitLVDS clock 1LVDS clock 2. . .LVDS clock LTA0D0_R2D1_R2. . .DL_R2TA1D0_R3D1_R3. . .DL_R3TA2D0_R4D1_R4. . .DL_R4TA3D0_R5D1_R5. . .DL_R5TA4D0_R6D1_R6. . .DL_R6TA5D0_R7D1_R7. . .DL_R7TA6D0_G2D1_G2. . .DL_G2TB0D0_G3D1_G3. . .DL_G3TB1D0_G4D1_G4. . .DL_G4TB2D0_G5D1_G5. . .DL_G5TB3D0_G6D1_G6. . .DL_G6TB4D0_G7D1_G7. . .DL_G7TB5D0_B2D1_B2. . .DL_B2TB6D0_B3D1_B3. . .DL_B3TC0D0_B4D1_B4. . .DL_B4TC1D0_B5D1_B5. . .DL_B5TC2D0_B6D1_B6. . .DL_B6TC3D0_B7D1_B7. . .DL_B7TC4HsyncHsync. . .HsyncTC5VsyncVsync. . .VsyncTC6DEDE. . .DETD0D0_R0D1_R0. . .DL_R0TD1D0_R1D1_R1. . .DL_R1TD2D0_G0D1_G0. . .DL_G0TD3D0_G1D1_G1. . .DL_G1TD4D0_B0D1_B0. . .DL_B0TD5D0_B1D1_B1. . .DL_B1TD6EmptyEmpty. . .Emptywherein TA0 . . . TA6, TB0 . . . TB6, TC0 . . . TC6; and TD0 . . . TD6, denote the 7 bits of first, second, third, and fourth LVDS data channels, respectively; D0_R0 . . . D0_R7 denote 8 respective bits of the red component of a first pixel; D0_G0 . . . D0_G7 denote 8 respective bits of the green component of the first pixel; D0_B0 . . . D0_B7 denote 8 respective bits of the blue component of the first pixel; D1_R0 . . . D1_R7 denote 8 respective bits of the red component of a second pixel; D1_Gob . . . D1_G7 denote 8 respective bits of the green component of the second pixel; D1_B0 . . . D1_B7 denote 8 respective bits of the blue component of the second pixel; DL_R0 . . . DL_R7 denote 8 respective bits of the red component of an L-th pixel; DL_G0 . . . DL_G7 denote 8 respective bits of the green component of the L-th pixel; and DL_B0 . . . DL_B7 denote 8 respective bits of the blue component of the L-th pixel. In the transmission format of Table 1, data of only one pixel is transmitted during each LVDS clock cycle.
In a LCD system having a resolution of 1280*720 pixels, and operating at a refresh frequency of about 75 Hz, the pixel data may be provided to the LVDS transmitter at a pixel data rate of approximately 75 MHz. Accordingly, a single LVDS stream, e.g., operating at a LVDS clock of 135 Mhz may be used. In a LCD system having a resolution of 1920*1080 pixels, and operating at a refresh frequency of about 60 Hz, the pixel data may be provided at a pixel data rate of approximately 148.5 MHz.
Accordingly, in such a system it may be required to implement two LVDS streams, each operating at a LVDS clock of 135 MHz.